Typically, power combiners are used in RF transmitters to combine the output signals of parallel power amplifiers into one high power RF output signal for wireless transmission. In these known transmitter structures the signals are first amplified by the power amplifiers and then they are combined by a separate power combiner to produce a combined amplified signal for transmission. Depending upon the circuit architecture and signal format used, however, it becomes necessary to make trade-offs between reducing power losses and achieving isolation between input signals of the combiner.
The need for efficiency is a particularly important design factor for the highly integrated requirements of transceivers used for wireless local area networks (LANs) and employing modulation formats such as OFDM (Orthogonal Frequency Division Multiplex). Moreover, the assignee of this invention and application has developed signal modulation methods, using OFDM signal format, whereby information signals are deconstructed into independent component signals, these independent signals being more efficiently processed and modulated than the original information signals from which they derive, and then the independent signals are up-converted, amplified and combined prior to transmission. Use of such independent modulated signals presents additional challenges to achieving efficiency at the amplification/combination stages of the transmitter, however, because the conventional model of amplification followed by combining, using known power amplifiers and combiners, is subject to inherent loss and isolation limitations.
The Chireix-type power amplifier, known to persons skilled in the art, represents one of the LINC (Linear amplification with Nonlinear Components) architectures and uses linear, saturated, or switch-mode amplifiers to provide amplification for signals having amplitude as well as phase modulation. It operates by adjusting the phase applied to two amplifiers, and combining the outputs through a combiner to reintroduce the amplitude modulation. An appropriate combiner for the Chireix architecture not only reinserts the amplitude modulation to the signal, it also provides a dynamic adjustment of the load impedance presented to each amplifier (out-phasing). This out-phasing adjustment of the load impedances is such that the DC current through each active device decreases as the combined output amplitude decreases, thereby maintaining high efficiency.
Appropriate combiners for a Chireix-type amplifier do not provide any isolation between the outputs of the two amplifiers. One example of this is a “pseudo” balanced magnetic transformer (i.e. having no center tap to ground connection) connecting the individual amplifier outputs to the two terminals, Input 1 and Input 2, of the input winding 100, as shown in the prior art illustration of FIG. 1. Here the magnetic transformer effectively combines, in series, in the output winding 200, the signals from the individual amplifiers and, for efficiency, the outputs of the individual amplifiers must be low impedance voltage sources. However, it will be understood by the skilled reader that such use of a magnetic transformer inherently introduces significant loss due to the limited Q achievable for the coils on a semiconductor substrate.
Alternatively, the amplifiers in a Chireix-type amplifier architecture can, instead, be connected in parallel if an appropriate impedance transformation is incorporated, that is, if the low impedance voltage source outputs (i.e. the individual amplifier outputs) are transformed into high output impedance current sources. With such a transformation, the high output impedance current source outputs can be connected in parallel, thereby avoiding the need for a magnetic transformer. As known by persons skilled in the art, this transformation can be achieved with a quarter-wave length transmission line, also referred to as an impedance inverter, as shown in the prior art illustration of FIG. 2, wherein the characteristic impedance (Z0) of the two quarter-wave length transmission lines is set to match the output impedance of the amplifier stage to the desired load impedance.
Instead of using such a quarter-wave length transmission line, the impedance inversion (transformation) can also be achieved using a lumped element equivalent circuit, as known to persons skilled in the art. Such a lumped element equivalent for broadband may consist of a series inductor, L, and two shunt negative inductances of equal absolute value, −L, as shown by the prior art illustration of FIG. 3A. Here, a load impedance ZL is transformed into an input impedance Zin=ω2L2/ZL. Alternatively, the lumped element equivalent circuit shown by the prior art illustration of FIG. 3B could be used for such impedance transformation. As will be appreciated by the skilled reader, these negative inductances, −L, can be realized, for a limited bandwidth (spot frequency) application, with the use of shunt capacitances; however, this is not applicable for a practical Class F amplifier for which such impedance inversion is needed at each of the first, second and third harmonics. Consequently, the realization of such a transformation for Class F amplifier circuits presents an obstacle for the practical design and implementation of such a circuit.
As illustrated by FIG. 4, the known switched-mode Class F amplifier provides a good approximation to a voltage square-wave across the output terminals of an active device 300 (the active device being a transistor in the usual case connected at its source, through a bias inductor 307, to a voltage rail 305) by “shorting” all even-harmonic voltages and “supporting” all odd-harmonic voltages. As a result, the voltage waveform across the output terminals of the active device 300 contains only odd-harmonic components. In addition, this sorting of odd- and even-harmonics results in a current passing through the output terminals of the active device 300 that contains the fundamental, and only even-harmonic components. Such “shorting” and “supporting” of the even and odd harmonics, respectively, is conveniently achieved, up to the third harmonic, with a series resonant circuit 310, 320 tuned to the second harmonic connected across the active device's output terminals, and a parallel resonant circuit 330 and 340 at the third harmonic connected between the output terminal of the active device 300 and the load 350. In operation, the series resonator 310,320 effectively shorts the second harmonic of the input signal (Vin) and supports the third harmonic of the input signal, while the parallel resonator 330,340 effectively blocks the third harmonic of the input signal from the load 350. Since each such harmonic component contains only a voltage component or a current component, the active device 300 does not absorb power other than at the fundamental frequency. Accordingly, as a result of the second and third harmonic resonators, only (approximately) the fundamental frequency signal reaches the load 350 at output terminal 351.
From a practical perspective, it is known that using such resonator circuits to process the input signal only up to its third harmonic components can provide a power-added efficiency of up to about 90%. However, it is also known that this Class F amplifier circuit architecture, where used at high frequencies, presents a design problem relating to the resonator circuits in that a source-drain (emitter-collector) parasitic capacitance results across the active device and causes the resonance values of these resonators to detune. In turn, this means that some level of amplitude for all harmonics of the voltage and current will exist, in practice, at such high frequencies.
By reason of the foregoing limitations, for a Class F, Chiriex-type amplifier architecture there exists a need for new and efficient means to achieve power amplification and combining of modulated signals in transmitters.